View MAX1998_1934599.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max1997/MAX1998 provide the voltages required for active-matrix, thin-film transistor liquid-crystal displays (tft lcds). both combine a high-performance step-up regulator with two linear-regulator controllers, input pro- tection switch control, and flexible sequence program- ming. the max1997 contains two additional linear- regulator controllers and a vcom buffer. the max1997/ MAX1998 can operate from input supplies of 2.7v to 5.5v and feature multiple levels of protection circuitry, making them complete power-supply systems for displays. the main dc-dc converter provides the regulated supply voltage for the display? source-driver ics. the converter is a high-frequency (up to 1.5mhz) step-up regulator with an integrated 14v n-channel mosfet that allows the use of ultra-small inductors and ceramic capacitors while achieving efficiencies over 85%. its current-mode control architecture provides fast transient response to pulsed loads. internal soft-start and cycle-by-cycle current limit help prevent input surge currents. the positive and negative linear-regulator controllers postregulate charge-pump outputs for tft gate-on and gate-off supplies. both linear-regulator controllers, as well as the step-up regulator, have supply-sequencing control inputs. the three outputs can be sequenced in any order by selecting the appropriate external components. the max1997 features a high-current backplane driver (vcom). this buffer provides peak currents exceeding 300ma (typ) and requires only a 0.47? output filter capacitor. the max1997? two additional linear-regulator controllers can be used to build the gamma reference voltage and a logic supply. the max1997/MAX1998 have a unique input switch con- trol that can replace the typical input supply fuse. when a fault is detected, the regulator is disconnected from the input supply. the fault detector monitors all the regulated output voltages and the current from the input supply. in addition, the max1997/MAX1998 enter shutdown when the internal over-temperature threshold is reached. the max1997 is available in a 32-pin thin qfn package and the MAX1998 is available in a 20-pin thin qfn pack- age. both packages have a maximum thickness of 0.8mm suitable for ultra-thin lcd panels. applications notebook computer displays lcd monitors car navigation displays features 2.7v to 5.5v input supply range adjustable (up to +13v) output voltage for source-driver ics integrated high-efficiency power mosfet linear-regulator controllers for tft gate-on and gate-off supplies high-current vcom buffer (max1997 only) two additional linear-regulator controllers (max1997 only) programmable power-up sequencing multiple overload protection with thermal shutdown 1? shutdown current 32-pin/20-pin thin qfn packages max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer ________________________________________________________________ maxim integrated products 1 19-2638; rev 0; 10/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin-package max1997 etj -40 c to +85 c 32 thin qfn 5mm x 5mm MAX1998 etp -40 c to +85 c 20 thin qfn 5mm x 5mm freq in gate ocp ocn drvn fbn drva ref gnd fb fbp drvp lx on2 onp onn ct pgnd tgnda top view 20 19 18 17 16 13 12 11 14 15 4 3 2 1 5 6 7 8 9 10 MAX1998 thin qfn 5mm 5mm pin configurations pin configurations continued at end of data sheet.
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, shdn , fb, fbp, fbn, fb1, fb2, ondc, onp , onn , on2 , tgnda, tgndb to gnd.............-0.3v to +6v pgnd to gnd ..................................................................... 0.3v lx, v ddb to gnd....................................................-0.3v to +14v drvp, drv1, drv2, drva to gnd .......................-0.3v to +30v ref, freq, gate, ocn, ocp, ct, pflt to gnd ..................................................-0.3v to v in + 0.3v drvn to gnd ..........................................v in - 28v to v in + 0.3v fbpb, fbnb, outb to gnd.......................-0.3v to v ddb + 0.3v outb continuous output current .................................. 100ma max1997 continuous power dissipation (t a = +70 c) 32-pin thin qfn (derate 21.2mw/ c above +70 c) ............................1702mw MAX1998 continuous power dissipation (t a = +70 c) 20-pin thin qfn (derate 20mw/ c above +70 c) ...............................1600mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (circuit of figure 1, v in = 3v, v ddb = 10v, shdn = ondc = freq = in, c ref = 0.22f, pgnd = gnd, t a = 0? to +85? . typical values are at t a = +25 c, unless otherwise noted.) parameter conditions min typ max units in supply range 2.7 5.5 v v in rising 2.5 2.7 2.9 in undervoltage lockout threshold 350mv (typ) hysteresis v in falling 2.2 2.35 2.5 v v fb = v fbp = v fb1 = v fb2 = 1.5v, v fbn = 0 (max1997 only) 0.54 1.25 in quiescent current (note 1) v fb = v fbp = 1.5v, v fbn = 0 (MAX1998 only) 0.476 1 ma in shutdown current v shdn = 0, v in = 5.5v 0.1 1 a -2a < i ref < 50a 1.231 1.250 1.269 ref output voltage -2a < i ref < 75a 1.225 1.250 1.275 v thermal shutdown 160 c overcurrent comparator input offset voltage v ocn = v ocp = 1.5v to 0.8v v in -5 +5 mv input bias current v ocn = v ocp = 0.8v v in -50 +50 na ocn, ocp input common-mode range 1.5 0.8 v in v fault timer pflt = gnd (max1997 only) 21.8 pflt unconnected (max1997 only) 43.6 fault timer period pflt = in, or MAX1998 87.2 ms gate output sink current during slew v gate = 1.5v during turn-on transition 5 10 15 a gate output pulldown resistance v gate < 0.5v 200 ? gate output pullup resistance 200 ? main step-up regulator output voltage range v in 13 v freq = in 1.5 freq unconnected 0.637 0.75 0.863 operating frequency freq = gnd 0.375 mhz
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v in = 3v, v ddb = 10v, shdn = ondc = freq = in, c ref = 0.22f, pgnd = gnd, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter conditions min typ max units oscillator maximum duty cycle 80 85 90 % fb regulation voltage i lx = 200ma 1.229 1.242 1.254 v fb fault trip level v fb falling 0.96 1.00 1.04 v fb load regulation i main = 0 to full load -1.6 % fb line regulation v in = 2.7v to 5.5v 0.2 0.4 %/v fb input bias current v fb = 1.5v -100 +100 na lx on-resistance 250 450 m ? lx leakage current v lx = 13v 0.01 20 a lx current limit 1.6 2.1 2.8 a lx rms current rating (note 2) 1.4 a soft-start period 4096/f osc s soft-start step size v ref /32 v positive linear-regulator controllers (reg p, reg 1, and reg 2) i drvp = 100a i drv1 = 1350a (max1997 only) fb_ regulation voltage i drv2 = 335a (max1997 only) 1.225 1.250 1.275 v fb_ fault trip level v fb _ falling 0.96 1.00 1.04 v fb_ input bias current v fb _ = 1.25v -250 +250 na v drvp = 10v, i drvp = 0.05ma to 1ma v drv1 = 10v, i drv1 = 0.5ma to 5ma (max1997 only) fb_ effective load regulation error (transconductance) v drv2 = 10v, i drv2 = 0.1ma to 2ma (max1997 only) -1.5 -2 % i drvp = 100a, 2.7v < v in < 5.5v i drv1 = 1350a, 2.7v < v in < 5.5v (max1997 only) fb_ line (in) regulation error i drv2 = 335a, 2.7v < v in < 5.5v (max1997 only) 1 mv bandwidth (note 2) 1000 khz drvp sink current 2 3.3 drv1 sink current (max1997 only) 5 18 drv2 sink current (max1997 only) v fb _ = 1.1v, v drv _ = 10v 5 15 ma drv_ leakage current v fb _ = 1.5v, v drv _ = 28v 0.1 10 a soft-start period 4096/f osc s soft-start step size v ref /32 v negative linear-regulator controller (reg n) fbn regulation voltage i drvn = 100a 95 125 155 mv fbn fault trip level v fbn rising 325 370 475 mv fbn input bias current v fbn = 0v -200 +200 na
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 3v, v ddb = 10v, shdn = ondc = freq = in, c ref = 0.22f, pgnd = gnd, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.) parameter conditions min typ max units fbn effective load regulation error (transconductance) v drvn = -10v, i drvn = 50a to 1ma 18 25 mv fbn line (in) regulation error i drvn = 100a, 2.7v < v in < 5.5v 1 mv bandwidth (note 2) 1000 khz drvn source current v fbn = 200mv, v drvn = -10v 2 4.2 ma drvn leakage current v fbn = -0.1v, v drvn = -20v 0.1 10 a soft-start period 4096/f osc s soft-start step size v ref /32 v vcom buffer (max1997 only) v ddb supply range 4.5 13 v v ddb supply current v fbpb = v fbnb = 5v, v ddb = 9v 367 900 a v ddb shutdown current v ddb = 13v, shdn = ondc = gnd 3.5 13 a input offset voltage v fbpb = 2.5v, no load -5 +5 mv input bias current v fbpb = v fbnb = 1.2v to v ddb - 1.2v 1 a input offset current v fbpb = v fbnb = 1.2v to v ddb - 1.2v -100 +100 na input common-mode range v ddb = 4.5v to 13v 1.2 v ddb - 1.2 v power-supply rejection ratio v ddb = 4.5v to 13v, v fbpb = 2.25v 70 db common-mode rejection ratio v fbpb = v fbnb = 1.2v to v ddb - 1.2v 70 db gain-bandwidth product small signal 1/6 c l hz load-transient settling time r l = 25 ? , c l = 10nf, v drive = 9v, settle to within 10mv (note 4) 5 s small signal ( 1mv overdrive) 0.3 transconductance large signal ( 30mv overdrive) 7.2 s output current drive 100mv overdrive, v outb = 3v or 7v 150 300 ma logic signals ( shdn , ondc) input low voltage 100mv typ hysteresis 0.4 v input high voltage 1.6 v input current 0.01 1 a control inputs and outputs onn , onp , on2 comparator offset v o n _ - v ct , v ct = 1.25v 50mv -50 +50 mv drva sink current v drva = 10v, v ct = 1.25v, v on2 = 2v 5 11 ma drva off-leakage v drva = 28v, v ct = 1.25v, v on2 = 1v 0.1 10 a ct source current v ct = 1v 2.5 5 7.5 a ct discharge resistance v ct = 1v 15 100 ? freq, pflt input low voltage 1v freq, pflt input middle voltage v in /2 freq, pflt input high voltage v in - 1 v freq, pflt input current freq, pflt = gnd or in -50 +50 a
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer _______________________________________________________________________________________ 5 electrical characteristics (v in = 3v, v ddb = 10v, shdn = ondc = freq = in, c ref = 0.22f, pgnd = gnd, t a = -40 c to +85 c , unless otherwise noted.) (note 3) parameter conditions min typ max units in supply range 2.7 5.5 v v in rising 2.5 2.9 in undervoltage lockout threshold 350mv typ hysteresis v in falling 2.2 2.5 v v fb = v fbp = v fb1 = v fb2 = 1.5v, v fbn = 0 (max1997 only) 1.25 in quiescent current (note 1) v fb = v fbp = 1.5v, v fbn = 0 (MAX1998 only) 1 ma -2a < i ref < 50a 1.223 1.270 ref output voltage -2a < i ref < 75a 1.218 1.280 v overcurrent comparator input offset voltage v ocn = v ocp = 1.5v to 0.8v v in -5 +5 mv input bias current v ocn = v ocp = 0.8v v in -50 +50 na ocn, ocp input common-mode range 1.5 0.8 v in v main step-up regulator output voltage range v in 13 v freq = in 1 2 freq unconnected 0.563 0.937 operating frequency freq = gnd 0.25 0.50 mhz oscillator maximum duty cycle 78 92 % fb regulation voltage i lx = 200ma 1.215 1.260 v fb fault trip level v fb falling 0.96 1.04 v fb input bias current v fb = 1.5v -100 +100 na lx on-resistance 450 m ? lx current limit 1.6 2.8 a positive linear-regulator controllers (reg p, reg 1, and reg 2) i drvp = 100a i drv1 = 1350a (max1997 only) fb_ regulation voltage i drv2 = 335a (max1997 only) 1.213 1.288 v fb_ fault trip level v fb _ falling 0.96 1.04 v v drvp = 10v, i drvp = 0.05ma to 1ma v drv1 = 10v, i drv1 = 0.5ma to 5ma (max1997 only) fb_ effective load regulation error (transconductance) v drv2 = 10v, i drv2 = 0.1ma to 2ma (max1997 only) -2.5 % drvp sink current 1 drv1 sink current (max1997 only) 5 drv2 sink current (max1997 only) v fb _ = 1.1v, v drv _ = 10v 5 ma
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 6 _______________________________________________________________________________________ electrical characteristics (continued) (v in = 3v, v ddb = 10v, shdn = ondc = freq = in, c ref = 0.22f, pgnd = gnd, t a = -40 c to +85 c , unless otherwise noted.) (note 3) parameter conditions min typ max units negative linear-regulator controller (reg n) fbn regulation voltage i drvn = 100a 95 155 mv fbn fault trip level v fbn rising 325 475 mv fbn effective load regulation error (transconductance) v drvn = -10v, i drvn = 0.05ma to 5ma 30 mv drvn source current v fbn = 200mv, v drvn = -10v 1 ma vcom buffer (max1997 only) v ddb supply range 4.5 13 v v ddb supply current v fbpb = v fbnb = 5v, v ddb = 9v 900 a input offset voltage v fbpb = 2.5v, no load -5 +5 mv input bias current v fbpb = v fbnb = 1.2v to v ddb - 1.2v 1 a input common-mode range v ddb = 4.5v to 13v 1.2 v ddb - 1.2 v out current drive 100mv overdrive, v outb = 3v or 7v 150 ma logic signals ( shdn , ondc) input low voltage 100mv typ hysteresis 0.4 v input high voltage 1.6 v control inputs and outputs freq, pflt input low voltage 1v freq, pflt input high voltage v in - 1 v freq, pflt input current freq, pflt = gnd or in -50 +50 a note 1: quiescent current does not include switching losses. note 2: guaranteed by design, not production tested. note 3: specifications to -40 c are guaranteed by design, not production tested. note 4: the vcom buffer load transient settling time is measured with the following circuit: max1997 20k ? 20k ? r l 25 ? c l 10nf fbpb v ddb gnd 1 f 1 f outb fbnb v gamma 8.6v v source 9v v x v drive 8v
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer _______________________________________________________________________________________ 7 typical operating characteristics (circuit of figure 1, v in = 3.3v, v main = 9v, v g_on = 20v, v g_off = -7v, v logic = 2.5v, v gamma = 8.6v, t a = +25 c, unless otherwise noted.) step-up regulator efficiency vs. load current (v main = 9v) max1997 toc01 load current (ma) efficiency (%) 100 10 10 20 30 40 50 60 70 80 90 100 0 1 1000 v in = 2.7v v in = 3.3v v in = 5.5v step-up regulator output voltage vs. load current (v main = 9v) max1997 toc02 load current (ma) output voltage (v) 100 10 8.6 8.7 8.8 8.9 9.0 9.1 8.5 1 1000 v in = 2.7v v in = 3.3v v in = 5.5v step-up regulator efficiency vs. load current (v main = 13v) max1997 toc03 load current (ma) efficiency (%) 100 10 10 20 30 40 50 60 70 80 90 100 0 1 1000 v in = 2.7v v in = 3.3v v in = 5.5v step-up regulator efficiency vs. load current max1997 toc04 load current (ma) efficiency (%) 100 10 10 20 30 40 50 60 70 80 90 100 0 1 1000 v in = 5.5v v in = 3.3v v in = 2.7v 750khz operation l = 4.7 h coilcraft lpo25061b-472 c out = 3 x 4.7 f/10v x7r ceramic step-up regulator switching frequency vs. input voltage max1997 toc05 input voltage (v) frequency (khz) 5.0 4.5 4.0 3.5 3.0 500 700 900 1100 1300 1500 1700 300 2.5 5.5 v main = 9v i main = 200ma frequency = v in frequency = open frequency = 0 step-up regulator normal operation (200ma load) max1997 toc06 1 s/div b a c 1a 10v 0 8.98v 9v 9.02v 0 5v a: v lx , 5v/div b: v main = 9v, 20mv/div, ac-coupled c: inductor current, 1a/div step-up regulator load transient response (without lag compensation, figure 1) max1997 toc07 10 s/div b a c 0.5a 200ma 0 1a 8.95v 9v 0 a: i main = 0 to 200ma, 200ma/div b: v main = 9v, 50mv/div, ac-coupled c: inductor current, 500ma/div
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 8 _______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, v in = 3.3v, v main = 9v, v g_on = 20v, v g_off = -7v, v logic = 2.5v, v gamma = 8.6v, t a = +25 c, unless otherwise noted.) step-up regulator load transient response (with lag compensation, figure 9) max1997 toc08 10 s/div b a c 0.5a 200ma 0 1a 8.9v 9v 0 a: i main = 0 to 200ma, 200ma/div b: v main = 9v, 50mv/div, ac-coupled c: inductor current, 500ma/div r7 = 76.8k ? , r8 = 12.1k ? , r10 = 1.5k ? , c10 = 470pf step-up regulator load transient response (2 s pulses) (without lag compensation, figure 1) max1997 toc09 4 s/div b a c 1a 1a 0 2a 8.9v 9v 50ma a: i main = 50ma to 1a, 1a/div b: v main = 9v, 100mv/div, ac-coupled c: inductor current, 1a/div step-up regulator load transient response (2 s pulses) (with lag compensation, figure 9) max1997 toc10 10 s/div b a c 1a 1a 0 2a 8.9v 9v 50ma a: i main = 50ma to 1a, 1a/div b: v main = 9v, 100mv/div, ac-coupled c: inductor current, 1a/div r7 = 76.8k ? , r8 = 12.1k ? , r10 = 1.5k ? , c10 = 470pf step-up regulator soft-start max1997 toc11 1ms/div b a c 5v 5v 0 10v 0 5v 0 a: v shdn , 5v/div b: v gate , 5v/div c: v drain , 5v/div d: v main , 5v/div d 5v 0 power-up sequence max1997 toc12 4ms/div b a c 0 10v -10v 0 10v 20v 0 a: v main , 10v/div b: v source , 10v/div c: v gate_on , 10v/div d: v gate_off , 10v/div v onn < v onp < v on2 d 10v 0 power-up sequence max1997 toc13 4ms/div b a c 0 10v -10v 0 10v 20v 0 a: v main , 10v/div b: v source , 10v/div c: v gate_on , 10v/div d: v gate_off , 10v/div v onn > v onp > v on2 d 10v 0
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer _______________________________________________________________________________________ 9 typical operating characteristics (continued) (circuit of figure 1, v in = 3.3v, v main = 9v, v g_on = 20v, v g_off = -7v, v logic = 2.5v, v gamma = 8.6v, t a = +25 c, unless otherwise noted.) reg p (gate-on voltage) load regulation max1997 toc14 load current (ma) output-voltage variation (%) 1 -0.20 -0.15 -0.10 -0.05 0 -0.25 0.1 10 reg n (gate-off voltage) load regulation max1997 toc15 load current (ma) output-voltage variation (%) 1 -0.32 -0.24 -0.16 -0.08 0 -0.40 0.1 10 reg 1 (logic supply) load regulation max1997 toc16 load current (ma) output-voltage variation (%) -0.8 -0.6 -0.4 -0.2 0 -1.0 1 1000 100 10 reg 2 (gamma reference) load regulation max1997 toc17 load current (ma) output-voltage variation (%) 1 -0.16 -0.12 -0.08 -0.04 0 -0.20 0.1 10 reg 1 (logic supply) load transient response max1997 toc18 40 s/div b a 2.49v 300ma 2.5v 0 100ma 200ma a: load current, 0 to 250ma, 100ma/div b: v logic = 2.5v, 10mv/div, ac-coupled reg 2 (gamma reference) v main transient rejection max1997 toc19 4 s/div b a 8.8v 20v 8.58v 8.60v 8.62v 0 a: v lx , 20v/div b: v gamma = 8.6v, 20mv/div, ac-coupled c: v main = 9v, 200mv/div, ac-coupled d: i main = 0 to 1a, 1a/div 0 1a 9.0v d c
typical operating characteristics (continued) (circuit of figure 1, v in = 3.3v, v main = 9v, v g_on = 20v, v g_off = -7v, v logic = 2.5v, v gamma = 8.6v, t a = +25 c, unless otherwise noted.) max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 10 ______________________________________________________________________________________ overcurrent protection response to overload during startup max1997 toc20 20ms/div b a c 0 10v -10v 10v 20v 0 5v a: v main , 5v/div b: v gate , 5v/div c: v g_on , 10v/div d: v g_off , 10v/div d 0 5v overcurrent protection response to overload during normal operation max1997 toc21 20ms/div b a c 0 10v -10v 10v 20v 0 5v a: v main , 5v/div b: v gate , 5v/div c: v g_on , 10v/div d: v g_off , 10v/div d 0 5v reference voltage vs. load current max1997 toc22 load current ( a) reference voltage (v) 10 1.247 1.248 1.249 1.250 1.246 1 100 lx current limit vs. input voltage max1997 toc23 input voltage (v) current limit (a) 5.0 4.5 4.0 3.5 3.0 1.8 1.9 2.0 2.1 2.2 1.7 2.5 5.5 t a = -40 c t a = +25 c t a = +85 c vcom buffer transconductance vs. temperature max1997 toc24 temperature ( c) transconductance (s) 80 60 40 20 0 -20 2 4 6 8 10 0 -40 100 large-signal transconductance small-signal transconductance vcom load transient response (circuit of page 6, note 4) max1997 toc25 4 s/div b a c 0 1a -20v 20v 3.4v 3.6v 0 a: load current, 1a/div b: v outb = 3.6v, 200mv/div, ac-coupled c: v x , 20v/div -1a 3.8v pin max1997 MAX1998 name function 1 tgndb internal connection. connect this pin to ground. do not leave this pin floating. 2 1 pgnd power ground. pgnd is the source of the n-channel power mosfet. connect pgnd to the star ground at the device s backside pad. 3 drv1 logic linear-regulator (reg 1) base drive. open drain of an internal n-channel mosfet. connect drv1 to the base of an external pnp linear regulator pass transistor. (see the pass transistor selection section). pin description
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer ______________________________________________________________________________________ 11 pin max1997 MAX1998 name function 4 fb1 logic linear-regulator (reg 1) feedback input. fb1 regulates at 1.25v nominal. connect fb1 to the center tap of a resistive voltage-divider between the reg 1 output and the analog ground (gnd) to set the output voltage. place the resistive voltage-divider close to the pin. 52ct sequence timing control input. connect a capacitor from this pin to gnd. this timing capacitor controls the turn-on of reg p, reg n, reg 2, and drva. the sequence timing block is enabled, together with the main step-up regulator, when ondc goes high. then an internal 5a current source charges the timing capacitor from 0v to v in , which sets the turn- on delay. a discharge switch keeps ct at gnd when the sequence timing block is disabled. (see the power-up sequencing and inrush current control section.) 63 onn gate-off linear-regulator (reg n) sequence control input. reg n is enabled when shdn is high, the gate to the input p-channel mosfet is low, ondc is high, and v ct > v o n n . (see the power-up sequencing and inrush current control section.) 74 onp gate-on linear-regulator (reg p) sequence control input. reg p is enabled when shdn is high, the gate to the input p-channel mosfet is low, ondc is high, and v ct > v onp . (see the power-up sequencing and inrush current control section.) 85 on2 gamma linear-regulator (reg 2) sequence control input. reg 2 is enabled when shdn is high, the gate to the input p-channel mosfet is low, ondc is high, and v ct > v o n 2 . on2 also controls the drva open-drain output, which is typically used to turn on an n-channel mosfet between the step-up regulator output and the source driver ics supply pins. (see the power-up sequencing and inrush current control section.) 9 6 drvn gate-off linear-regulator (reg n) base drive. open drain of an internal p-channel mosfet. connect drvn to the base of an external npn linear regulator pass transistor. (see the pass transistor selection section.) 10 7 fbn g ate- off li near - reg ul ator ( re g n ) feed b ack inp ut. fbn r eg ul ates to 125m v nom i nal . c onnect fbn to the center tap of a r esi sti ve vol tag e- d i vi d er b etw een the re g n outp ut and the r efer ence vol tag e ( re f) to set the outp ut vol tag e. p l ace the r esi sti ve vol tag e- d i vi d er cl ose to the p i n. 11 8 drva open-drain sequence output. the drva open-drain output is controlled by on2 . drva is typically used to turn on an n-channel mosfet between the step-up regulator output and the source-driver ics supply pins. drva is high impedance when shdn is high, the gate to the input p-channel mosfet is low, ondc is high, and v ct > v on2 . otherwise, drva connects to ground. (see the power-up sequencing and inrush current control section.) 12 9 ref internal reference bypass terminal. connect a 0.22f ceramic capacitor from ref to the analog ground (gnd). external load capability is at least 75a. 13 10 gnd analog ground. 14 fbnb vcom buffer inverting input. (see the vcom buffer section.) 15 outb vcom buffer output. requires a minimum 0.47f ceramic filter capacitor to gnd. place the capacitor as close as possible to outb. 16 v ddb vcom buffer supply input. bypass to gnd with a 0.47f capacitor as close as possible to the pin. 17 fbpb vcom buffer noninverting input. (see the vcom buffer section.) 18 fb2 gamma linear-regulator (reg 2) feedback input. fbp regulates to 1.25v nominal. connect fb2 to the center tap of a resistive voltage-divider between the reg 2 output and the analog ground (gnd) to set the output voltage. place the divider close to the pin. pin description (continued)
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 12 ______________________________________________________________________________________ pin max1997 MAX1998 name function 19 drv2 gamma linear-regulator (reg 2) base drive. open drain of an internal n-channel mosfet. connect drv2 to the base of an external pnp linear regulator pass transistor. (see the pass transistor selection section.) 20 11 fb main step-up regulator feedback input. connect fb to the center tap of a resistive voltage- divider between the main output (v main ) and the analog ground (gnd) to set the main step- up regulator output voltage. (see the main step-up regulator, output voltage selection section.) place the resistive voltage-divider close to the pin. 21 12 fbp g ate- on li near - reg ul ator ( re g p ) feed b ack inp ut. fbp r eg ul ates to 1.25v nom i nal . c onnect fbp to the center tap of a r esi sti ve vol tag e- d i vi d er b etw een the re g p outp ut and the anal og g r ound ( gn d ) to set the outp ut vol tag e. p l ace the r esi sti ve vol tag e- d i vi d er cl ose to the p i n. 22 13 drvp gate-on linear-regulator (reg p) base drive. open drain of an internal n-channel mosfet. connect drvp to the base of an external pnp linear-regulator pass transistor. (see the pass transistor selection section.) 23 14 lx switching node. drain of the internal n-channel power mosfet for the main step-up regulator. 24 15 tgnda internal connection. connect this pin to ground. do not leave this pin floating. 25 16 ocn overcurrent comparator inverting input. connect ocn to the center tap of a resistive voltage-divider connected to the drain of the external input protection p-channel mosfet. (see the input overcurrent protection section.) if unused, connect ocn to ref. 26 17 ocp overcurrent comparator noninverting input. connect ocp to the center tap of a resistive voltage-divider connected to the source of the external input protection p-channel mosfet. the voltage on ocp sets the input overcurrent threshold. (see the input overcurrent protection section.) if unused, connect ocp to gnd. 27 18 gate gate-drive output to the external input protection p-channel mosfet. (see the input overcurrent protection section.) if unused, leave gate unconnected. 28 pflt fault timer select input. pull pflt above its logic high threshold (0.7 v in ) to set the fault delay period to 87ms. pull pflt below its logic low threshold (0.3 v in ) to set the fault delay period to 22ms. leave pflt unconnected to set the fault delay period to 44ms. the fault delay period for the MAX1998 is fixed at 87ms. 29 19 in supply input. the supply voltage powers all the control circuitry. the input voltage range is from 2.7v to 5.5v. bypass in to gnd with a 0.47f ceramic capacitor. place the capacitor within 5mm of in. 30 ondc s tep - u p reg ul ator log i c c ontr ol inp ut. the step - up r eg ul ator , v c o m b uffer , and the seq uence ti m i ng b l ock ar e enab l ed w hen o n d c i s hi g h and d i sab l ed w hen on d c i s l ow . 31 20 freq frequency select input. pull freq above its logic high threshold (0.7 v in ) to set the main step-up regulator switching frequency to 1.5mhz. pull freq below its logic low threshold (0.3 v in ) to set the frequency to 375khz. leave freq unconnected to set the frequency to 750khz. 32 shdn active-low shutdown control input. all the sections of the device are disabled and the gate pin goes high when shdn is below its 0.4v logic low threshold. pull shdn above its 1.6v logic high threshold to enable the device. do not leave shdn unconnected. pin description (continued)
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer ______________________________________________________________________________________ 13 figure 1. standard application circuit v in 2.7v to 5.5v l1 3.0 h p1 r2 51.1k ? c2 10 f 6.3v r1 10 ? q1 v logic 2.5v c7 1000pf c8 100pf c1 0.47 f r5 150k ? r3 150k ? r88 12.4k ? r99 12.4k ? r77 510 ? r4 43.2k ? c12 1 f c13 10 f c18 0.1 f analog ground (gnd) power ground (pgnd) gate ocn lx fb ocp in shdn freq drv1 fb1 20 23 25 27 26 29 32 d1 v main 9v lx 31 3 4 r15 6.8k ? r18 6.8k ? r11 118k ? r12 20k ? r10 2.2k ? r7 7.68k ? r9 1m ? r8 1.21k ? r6 100k ? r16 150k ? r17 24.3k ? r21 39k ? r20 20k ? r14 20k ? r13 20k ? r19 301k ? r22 39k ? r23 39k ? d5 drvp fbp q3 lx 22 21 d3 d4 drv2 fb2 q2 v g_off -7v v g_on 20v 19 18 ondc 30 pflt 28 on2 onp onn fbnb outb fbpb v ddb 16 17 14 15 8 7 6 drva 11 n1 tgnda tgndb 24 1 drvn fbn lx q4 d2 9 10 c27 1000pf v source 9v ct ref gnd ref d6 ref 5 12 13 v vcom pgnd 2 v gamma 8.6v c17 0.22 f c16 0.1 f c20 0.47 f c26 1 f c19 0.1 f c24 0.1 f c25 0.1 f c22 0.1 f c14 2.2 f c15 1 f c11 0.47 f c9 0.01 f c4 4.7 f 10v c5 4.7 f 10v c6 4.7 f 10v c23 0.1 f max1997 r24 150k ? c28 1000pf
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 14 ______________________________________________________________________________________ figure 2. system functional diagram uvlo and gate control fbn drvn fbp drvp fb lx gate ocn ocp overcurrent comparator pgnd ondc on2 in shdn onp onn drva ct oc ref pflt freq drv1 fb1 drv2 fb2 v c v c v p v g_on v logic v source v source v main v main v p v in vcom buffer gnd vddb fbpb fbnb outb n v vcom v gamma v g_off max1997/MAX1998 max1997 only ref, osc, and bias sequence control reg 1 with soft-start and fault comparator reg 2 with soft-start and fault comparator reg n with soft-start and fault comparator reg p with soft-start and fault comparator main step-up regulator with soft-start and fault comparator control block control inputs n.c. n.c.
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer ______________________________________________________________________________________ 15 standard application circuit the standard application circuit (figure 1) of the max1997 is a complete power-supply system for tft liquid-crystal displays. the circuit generates 9v for source drivers, +20v and -7v for gate drivers, a 2.5v logic supply for the timing controller, a 8.6v gamma reference voltage, and a vcom buffer. the input voltage range is from 2.7v to 5.5v. table 1 lists the selected component options and table 2 lists the component suppliers. detailed description the max1997 and MAX1998 contain a high-perfor- mance step-up switching regulator, two low-cost linear- regulator controllers, and multiple levels of protection circuitry. the max1997 also includes two additional lin- ear-regulator controllers and a high-current vcom buffer. figure 2 shows the max1997/MAX1998 system functional diagram. the output voltage of the main step-up regulator (v main ) can be set from v in to 13v with an external resistive voltage-divider. high switch- ing frequency (375khz/750khz/1.5mhz) and current- mode control provide fast transient response and allow the use of low-profile inductors and ceramic capacitors. the low r ds(on) internal power mosfet minimizes the external component count and achieves high efficiency using a lossless current-sense architecture. two charge pumps take energy from the main step-up regulator s switching node (lx) to generate positive and negative supplies. additional capacitor and diode stages can be used to generate supply voltages greater than +35v and less than -15v. the positive and negative linear-regulator controllers postregulate the charge-pump supply voltages and allow users to program the power-up sequence as well. the high-current vcom buffer of the max1997 is ideal for driving the backplane of a tft lcd panel. it requires only a 0.47f ceramic output capacitor for stability. the max1997 s two additional linear-regulator controllers can be used to build the gamma reference and logic supply. the unique input switch control of the max1997/ MAX1998 senses the current drawn from the input power supply by monitoring the voltage drop across the input p-channel mosfet. the protection mosfet and all regulator outputs latch off if an overcurrent condition lasts for more than the fault timer period. table 1. selected component list designation description c2, c13 10f, 6.3v x5r ceramic capacitors (1206), tdk c3216x5r0j106m c4, c5, c6 4.7f, 10v x7r ceramic capacitors (1210), taiyo yuden lmk352bj475mf d1 1.0a, 30v schottky diode (s-flat), toshiba crs02 d2, d3, d4 200ma, 25v dual-series schottky diodes (sot23), fairchild bat54s d5, d6 200ma, 75v diode (sot23), fairchild mmbd4148 l1 3.0h, 1.3a inductor, sumida cls5d11hp-3r0nc n1 1.9a, 30v n-channel mosfet (supersot -3), fairchild fdn357p p1 2.4a, 20v p-channel mosfet (supersot-3), fairchild fdn304p q1 3a, 25v pnp bipolar transistor (supersot-3), fairchild fsb749 q2, q3 200ma, 40v pnp bipolar transistors (sot23), fairchild mmbt3906 q4 200ma, 40v npn bipolar transistor (sot23), fairchild mmbt3904 supplier phone fax website fairchild 408-822-2000 408-822-2102 www.fairchildsemi.com sumida 847-545-6700 847-545-6720 www.sumida.com taiyo yuden 800-348-2496 847-925-0899 www.t-yuden.com tdk 847-803-6100 847-390-4405 www.component.tdk.com toshiba 949-455-2000 949-859-3963 www.toshiba.com table 2. component suppliers supersot is a trademark of fairchild semiconductor.
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 16 ______________________________________________________________________________________ in addition, all outputs are monitored for fault conditions that last longer than the fault timer period. the device goes into a latched shutdown state, if the junction tem- perature of the device exceeds +160 c. main step-up controller the main step-up regulator switches at up to 1.5mhz, and employs a current-mode control architecture to maximize loop bandwidth and provide fast transient response to pulsed loads found in source drivers for tft lcd panels. in addition, the high switching fre- quency allows the use of low-profile inductors and ceramic capacitors to minimize the thickness of lcd panel designs. the integrated high-efficiency mosfet reduces the number of external components. the ic s built-in soft-start function controls the inrush current. depending on the input-to-output voltage ratio, the reg- ulator controls the output voltage and the power deliv- ered to the output by modulating the duty cycle (d) of the power mosfet in each switching cycle. the duty cycle of the mosfet is approximated by: on the rising edge of the internal clock, the controller sets a flip-flop, which turns on the n-channel mosfet (figure 3). the input voltage is applied across the inductor. the inductor current ramps up linearly, storing energy in a magnetic field. once the sum of the feedback voltage, slope-compensation, and current-feedback signals trip the multi-input pwm comparator, the mosfet turns off, and the flip-flop resets. since the inductor current is con- tinuous, a transverse potential develops across the induc- tor that turns on the diode (d1). the voltage across the inductor becomes the difference between the output volt- age and the input voltage. this discharge condition forces the current through the inductor to ramp back down, transferring the energy stored in the magnetic field to the output capacitor and the load. the mosfet remains off for the rest of the clock cycle. d v-v main in main v figure 3. main step-up converter functional diagram to fault logic 1.0v r s q refout refin clk lx pgnd soft-start reset dominant ilim comparator from oscillator current sense slope_comp v limit fb ref
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer ______________________________________________________________________________________ 17 positive linear-regulator controller, reg p the positive linear-regulator controller is an analog gain block with an open-drain n-channel output. it drives an external pnp pass transistor with a 6.8k ? base-to-emitter resistor (figure 1). its guaranteed base drive sink current is at least 2ma. the regulator is designed to deliver 20ma with an output capacitor of 1f. reg p is enabled when shdn is high, the gate to the input p-channel mosfet is low, ondc is high, v ct > v onp , and the soft-start of the main step-up regulator is complete. (see the power-up sequencing and inrush current control section.) each time it is enabled, the regulator goes through a soft-start routine that ramps up its reference input. note that the voltage rating of the drvp output is 28v. if higher voltages are present, an external cascode npn transistor should be used with the emitter connected to drvp, the base to v main , and the collector to the base of the pnp (figure 4). reg p is typically used to provide the tft lcd gate driver s gate-on voltage. a sufficient voltage can be produced using a charge-pump circuit as shown in figure 1. use as many stages as necessary to obtain the required output voltage. (see the selecting the number of charge-pump stages section.) negative linear-regulator controller, reg n the negative linear-regulator controller is an analog gain block with an open-drain p-channel output. it dri- ves an external npn pass transistor with a 6.8k ? base-to-emitter resistor (figure 1). its guaranteed base drive source current is at least 2ma. the regulator is designed to deliver 20ma with an output capacitor of 0.47f. reg n is enabled when shdn is high, the gate to the input p-channel mosfet is low, ondc is high, and v ct > v onn (see the power-up sequencing and inrush current control section). each time it is enabled, the regulator goes through a soft-start routine that ramps down its reference input. note that the voltage rating of the drvn output is v in - 28v. if lower voltages are present, an external cascode pnp transistor should be used with the emitter connected to drvn, the base to gnd, and the collec- tor to the base of the npn (figure 5). reg n is typically used to provide the tft lcd gate driver s gate-off voltage. a negative voltage can be pro- duced using a charge-pump circuit as shown in figure 1. use as many stages as necessary to obtain the required output voltage. (see the selecting the number of charge-pump stages section.) linear-regulator controller, reg 1 (max1997 only) the linear-regulator controller reg 1 is an analog gain block with an open-drain n-channel output. it drives an external pnp pass transistor with a 510 ? base-to-emitter resistor (figure 1). its guaranteed base-drive sink current is at least 5ma. the regulator is designed to deliver 300ma with an output capacitor of 10f. reg 1 is enabled when shdn is high and the gate to the input p-channel mosfet is low. (see the power-up sequencing and inrush current control section.) each time it is enabled, the regulator goes through a soft- start routine that ramps up its reference input. reg 1 is typically used to provide the tft lcd timing controller s logic supply. figure 4. using cascode npn for output voltages > 28v v p v main v g_on drvp fbp pnp pass transistor npn cascode transistor figure 5. using cascode pnp for output voltages < vin - 28v v n v g_off drvn fbn ref npn pass transistor pnp cascode transistor
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 18 ______________________________________________________________________________________ linear-regulator controller reg 2 (max1997 only) the linear-regulator controller reg 2 is an analog gain block with an open-drain n-channel output. it drives an external pnp pass transistor with a 2.2k ? base-to-emitter resistor (figure 1). its guaranteed base drive sink current is at least 5ma. the regulator is designed to deliver 30ma with an output capacitor of 2.2f. reg 2 is enabled when shdn is high, the gate to the input p-channel mosfet is low, ondc is high, and v ct > v on2 . (see the power-up sequencing and inrush current control section.) each time it is enabled, the regulator goes through a soft-start routine that ramps up its reference input. reg 2 is typically used to provide the tft lcd gamma reference voltage. vcom buffer (max1997 only) the max1997 includes a vcom buffer, which is an oper- ational transconductance amplifier that provides a current output for driving the backplane of a tft lcd panel. the unity-gain bandwidth of this current-output buffer is: gbw = g m /c out where g m is the amplifier s transconductance, which is the ratio of the output current to the input voltage. the vcom buffer requires only a 0.47f ceramic output capacitor for stability. the bandwidth is inversely pro- portional to the output capacitance. thus, large capaci- tive loads reduce the bandwidth of the buffer output. in order to improve the transient response time, the ampli- fier has nonlinear transconductance. the amplifier senses the output current and increases the transconductance as the output current increases. the effect is to provide additional output current when the load demands it. undervoltage lockout (uvlo) to ensure that the input voltage is high enough for reli- able operation, the max1997/MAX1998 include an undervoltage lockout (uvlo) circuit. the uvlo thresh- old at the in pin is 2.7v (typ) rising and 2.35v (typ) falling. the 350mv (typ) hysteresis prevents supply tran- sients from causing a restart. once the input voltage exceeds the uvlo rising threshold, the controller enables the reference block. once the reference is above 1.05v, an internal 10a current source pulls the gate pin low and turns on an external p-channel mosfet switch (p1, figure 1) that connects the input supply to the regulator. when the input voltage falls below the uvlo falling threshold, the controller turns off the ref- erence and all the regulator outputs, and pulls gate high with an internal 100 ? switch to turn off p1 (figure 6). reference voltage (ref) the reference output is nominally 1.25v, and can source up to 75a. (see the typical operating characteristics. ) bypass ref with a 0.22f ceramic capacitor connected between ref and gnd. oscillator frequency control (freq) the internal oscillator frequency is adjustable using the three-level freq input. connect freq to ground for 375khz operation, connect freq to v in for 1.5mhz operation, and leave freq unconnected for 750khz operation. when freq is left unconnected, bypass freq to ground with a 1000pf to 0.1f capacitor to prevent switching noise from coupling into the pin s high input impedance. note that the soft-start period scales with the oscillator frequency. (see the soft-start section.) the fault timer period does not scale with the oscillator frequency. figure 6. external p-channel mosfet input switch control v ref 2 in gate v in input cap external pfet inductor input cap 10 a gate enable
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer ______________________________________________________________________________________ 19 shutdown ( shdn ) a logic-low signal on the shdn pin disables all device functions including the reference. during shutdown, the supply current drops to 0.1a (typ) to maximize battery life. the output capacitance, feedback resistors, and load current determine the rate at which each output voltage decays. a logic-high signal on the shdn pin activates the max1997/MAX1998. (see the power-up sequencing section.) do not leave the shdn pin floating. toggling shdn (below 0.4v) or cycling in (below 2.2v) clears the fault latch. power-up sequencing and inrush current control once shdn is pulled high and the input voltage on in exceeds the rising input uvlo threshold (2.7v typ), the reference turns on. with a 0.22f ref bypass capacitor, the reference reaches its regulation voltage of 1.25v in approximately 1ms. when the reference voltage is ready, the max1997/MAX1998 enable the oscillator and fault detector. after the oscillator is enabled, the controller turns on the external p-channel mosfet p1 (figure 1) by pulling gate low. the gate is pulled down with a 10a current source. add a capacitor from the gate of p1 to its drain to slow down the turn-on rate of the mosfet, which reduces inrush current. to guarantee slow turn-on at lower v in , add a series resistor between the gate pin and the gate of the exter- nal p-channel mosfet. the typical value of the resistor ranges between 100k ? and 200k ? . once gate reaches approximately 0.6v, an internal n-channel mosfet turns on and pulls gate to ground in order to maximize the enhancement of the external p-channel mosfet. after p1 fully turns on, reg 1 and the fault counter are enabled. a logic-high signal on ondc enables the main step-up regulator and the sequence control block. the sequence control state diagram is shown in figure 7. the unique sequence control block allows the positive gate-driver voltage (v g_on ), negative gate-driver volt- age (v g_off ), and the source-driver supply voltage (v source ) to be turned on in any order. the capacitor at the ct pin is kept discharged until the main step-up regulator is enabled. an internal 5a current source starts charging the ct capacitor and the ct voltage ramps linearly up to approximately v in . reg p, reg n, and reg 2 are enabled when the ct voltage exceeds their associated on_ control inputs. in addition, the positive linear regulator waits for the completion of the main step-up regulator soft-start. the positive linear regulator is controlled by onp . the negative linear reg- ulator is controlled by onn . reg2 and the open-drain output drva are controlled by on2 . the drva signal can be used to turn on an external n-channel mosfet (n1, figure 1), which connects the main step-up regu- lator output to the source driver s supply pins. soft-start each positive regulator (main, reg p, reg 1, and reg 2) includes a 5-bit soft-start dac whose input is the ref- erence, and whose output is st epped in 32 steps from zero up to the reference voltage. the soft-start dac of the negative regulator (reg n) steps from the reference down to 125mv in 32 steps. the soft-start duration scales with the switching frequency selected and is 2.73ms for 1.5mhz operation, 5.46ms for 750khz operation, and 10.92ms for 375khz operation. figure 7. power-up sequence state diagram shutdown shdn = 1 and v in present v in > 2.7v v in < 2.7v shdn = 0 or v in not present v in < 2.7v v ct > on2 v ct < on2 v ct < onp boost soft-start done and v ct > onp v ct < onn v ct > onn enable ref, bias, and uvlo enable osc, oc comp, gate clear fault enable reg 1 and fault counter enable boost, vcom, sequence block enable reg n enable reg p enable reg 2, drva high impedance gate ready gate not ready gate not ready ondc = 1 ondc = 0 ondc = 0 ondc = 0
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 20 ______________________________________________________________________________________ input overcurrent protection the high-side overcurrent comparator of the max1997/MAX1998 provides input overcurrent protec- tion when it is used together with the external p-channel mosfet switch p1 (figure 1). connect resistive volt- age-dividers from the source and drain of p1 to gnd to set the overcurrent threshold. the center taps of the dividers are connected to the overcurrent comparator inputs (ocn and ocp). see setting the input overcurrent threshold section for information on calcu- lating the resistor values. an overcurrent event acti- vates the fault-protection circuitry. (see the fault protection section.) fault protection during steady-state operation, if the output of the main regulator or any of the linear-regulator outputs is below its respective fault detection threshold, or an input over- current condition occurs, the max1997/MAX1998 acti- vate an internal fault timer (figure 8). if any condition or the combination of conditions indicates a continuous fault for the fault timer duration (see table 3), the max1997/MAX1998 set the fault latch, shutting down all the outputs except the reference and the oscillator. the fault detection circuit is disabled during the soft- start time of each regulator. once the fault condition is removed, toggle shdn (below 0.4v) or cycle the input voltage (below 2.2v) to clear the fault latch and reacti- vate the device. thermal shutdown the thermal shutdown feature limits total power dissipa- tion in the max1997/MAX1998. if the junction tempera- ture t j exceeds +160 c, a thermal sensor immediately activates the fault protection (figure 2) and sets the fault latch, which shuts down all the outputs except the reference, allowing the device to cool down. once the device cools down by at least 15 c, the fault latch can be cleared to reactivate the device. toggling shdn (below 0.4v) or cycling the input voltage (below 2.2v) clears the fault latch. design procedure main step-up regulator output voltage selection set the output voltage by connecting a resistive volt- age-divider from the output (v main ) to gnd with the center tap connected to fb (see figure 1). select r8 to be 1.5k ? or less for optimized transient response. for higher efficiency, increase r8 to 12k ? and add lag compensation. (see the feedback compensation sec- tion.) calculate r7 with the following equation: r7 = r8 [(v main / v fb ) - 1] where v fb = 1.242v - (d x 20mv) and d (v main - v in ) / v main . for example, if v in = 3v and d 0.66, then v fb = 1.229v. choosing 1.21k ? for r8, r7 is 7.65k ? . use 7.68k ? for r7. v main can range from v in to 13v. inductor selection the minimum inductance value, peak current rating, series resistance, and size are factors to consider when selecting the inductor. these factors influence the con- verter s efficiency, maximum output load capability, tran- sient response time, and output voltage ripple. for a switching frequency of 1.5mhz, use values between 1.8h and 4.7h. for a switching frequency of 750khz, use values between 3.3h and 8.2h. for a switching frequency of 375khz, use values between 6.8h and 15h. freq pin pflt pin* fault timer duration (clock cycles) fault timer duration (ms) gnd gnd 2 13 21.8 unconnected gnd 2 14 21.8 in gnd 2 15 21.8 gnd unconnected 2 14 43.6 unconnected unconnected 2 15 43.6 in unconnected 2 16 43.6 gnd in** 2 15 87.2 unconnected in** 2 16 87.2 in in** 2 17 87.2 table 3. fault timer duration * for max1997 only. ** the MAX1998 has pflt internally connected high.
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer ______________________________________________________________________________________ 21 the maximum inductor current, input voltage, output voltage, and switching frequency determine the induc- tor value. to ensure an adequate inductor current- sense signal in the ic, always calculate the inductor value with the maximum guaranteed inductor current even though the actual operating current may be much lower. for the max1997/MAX1998, the maximum guar- anteed inductor current is the minimum value of the internal lx current limit (1.6a, see the electrical characteristics ). the equations provided here include a constant defined as lir, which is the ratio of the peak- to-peak inductor current ripple to the average dc inductor current. for a good compromise between the size of the inductor, power loss, and output voltage rip- ple, select an lir of 0.3 to 0.5. the inductance value is then given by: where f osc is the oscillator frequency (see elec- trical characteristics ), and i l(max) is 1.6a. considering the typical application circuit, the typical input voltage is 3.3v, the main output voltage is 9v, and the switching frequency is 1.5mhz. based on the above equations, the inductance value is 4.3h for an lir of 0.2. the inductance value is 1.7h for an lir of 0.5. the induc- tance in the standard application circuit is chosen to be 3.3h. the inductor s peak current rating should be higher than the expected peak inductor current throughout the normal operating range. the expected peak inductor current is given by: where is the efficiency of the regulator. for most applications, the efficiency is between 75% and 85%. under fault conditions, the inductor current may reach the internal lx current limit (see electrical character- istics ). however, soft saturation inductors and the con- troller s fast current-limit circuitry protect the device from failure during such a fault condition. the inductor s dc resistance can significantly affect efficiency due to the resistive power loss (p lr ), which can be approximated by the following equation: where i lavg is the average inductor current and r l is the inductor s series resistance. for best performance, select inductors with resistance less than the internal n-channel mosfet s on-resistance (0.25 ? typ). to minimize radiated noise in sensitive applications, use a shielded inductor. pi r iv v r lr lavg l main main in l 2 2 =? ? ? ? ? ? ? i iv v 1 1 2 v v v-v lf peak main(max) main in(min) in(min) main main in(min) osc = ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? l v v v-v if 1 lir in(typ) main main in(typ) l(max) osc = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 8. startup and fault protection logic r s q shdn ondc gate enables reg 1 linear-regulator enables reg 2 linear-regulator enables step-up regulator enables reg p linear-regulator enables reg n linear-regulator uvlo reference ready thermal fault overcurrent fault reg 2 fault reg 1 fault reg p fault step-up regulator fault reg n fault f osc /128 freq clk gate ready step-up regulator soft-start done v ct > v on2 v ct > v onp v ct > v onn r ripple counter pflt fault timer fault latch
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 22 ______________________________________________________________________________________ output capacitor the output capacitor affects the circuit s stability and output-voltage ripple. a 15f ceramic capacitor works well in most 1.5mhz applications. depending on the output capacitor chosen, feedback compensation may be required or desirable to increase the loop phase margin or increase the loop bandwidth for transient response. (see the feedback compensation section.) the total output-voltage ripple has three components: the inductive ripple caused by the capacitor s equivalent series inductance (esl), the ohmic ripple due to the capacitor s equivalent series resistance (esr), and the capacitive ripple caused by the charging and discharg- ing of the output capacitance. since the esl is usually very small, the inductive ripple can be neglected: where i peak is the peak inductor current. (see the inductor selection section.) for ceramic capacitors, the output voltage ripple is typically dominated by v rip- ple(c) . the voltage rating and temperature characteris- tics of the output capacitor must also be considered. feedback compensation feedback compensation is not needed for the excellent stability and fast transient response of figure 1 s circuit. however, lead or lag compensation can be useful to compensate for layout issues, or optimize the transient response for various output capacitor or inductor values. the loop stability of a current-mode step-up regulator can be analyzed by using a small-signal model. in continuous conduction mode, the loop gain transfer function consists of a dc loop gain, a dominant pole, a right-half-plane (rhp) zero, and an esr zero. in the case of ceramic out- put capacitors, the esr zero is at very high frequency and can be ignored. for stable operation, place the domi- nant pole at a low enough frequency to ensure that the loop gain reaches unity well before the rhp zero, prefer- ably below one-third of the rhp zero frequency f z_rhp . the frequency of the dominant pole is: where r l is the load resistance and c is the output capacitance; the frequency of the rhp zero is: where d is the duty cycle and l is the inductance; and the dc gain is given by: where r cs is the 20m ? internal equivalent current- sense resistor, and r7 and r8 are the feedback divider resistors in figure 9. adding lead compensation (an rc network from v main to fb) increases the loop bandwidth, which can increase the speed of response to transients. too much speed can destabilize the loop and is not needed or recom- mended for figure 1 s components. lead compensation adds a zero-pole pair, providing gain at higher frequencies and increasing loop band- width. the frequencies of the zero and pole for lead compensation depend on the feedback divider resistors and the rc network between v main and fb (figure 9). a2 r dc cs l = + ? ? ? ? ? ? ? 0 8 78 1 log () r rr d r f z_rhp l = ? ( ) 1 2 2 d r l f 1 p_dominant l = 2 rc vv v vira v i c v-v vf ripple ripple(esr) ripple(c) ripple(esr) peak esr(cout) ripple(c) main out main in main osc =+ ? ? ? ? ? ? ,nd figure 9. external compensation v main v in r10 r8 r9 r l c9 lx fb gnd pgnd d1 c10 c r7 d l max1997 MAX1998
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer ______________________________________________________________________________________ 23 the frequencies of the zero and pole for the lead com- pensation are: at high frequencies, r9 is effectively in parallel with r7, determining the amount of added high-frequency gain. if r9 is very large, there is no added gain and as r9 approaches zero, the added gain approaches the inverse of the feedback divider s attenuation. a typical value for r9 is greater than half of r7. the value of c9 determines the frequency placement of the zero and pole. a typical value of c9 is between 100pf and 10nf. when adding lead compensation, always check the loop stability by monitoring the transient response to a pulsed output load. adding lag compensation (an rc network from fb to ground) decreases the loop bandwidth and improves fb noise immunity. lag compensation slows the tran- sient response but can increase stability margin, which can be needed for particular component choices, a poor layout, or high values of fb divider resistors (r8 greater than 1.5k ? ). lag compensation adds a pole-zero pair, attenuating gain at higher frequencies and lowering loop band- width. the frequencies of the pole and zero for lag com- pensation depend on the feedback divider resistors and the rc network between fb and gnd (figure 9). the frequencies of the pole and zero for the lag com- pensation are: at high frequencies, r10 is effectively in parallel with r8, increasing the divider attenuation ratio. if r10 is very large, the attenuation ratio remains unchanged and as r10 approaches zero, the attenuation ratio approaches infinity. a typical value for r10 is greater than 0.1 times r8. if high-value divider resistors are used, choose r10 < 1.5k ? for fb noise immunity. the value of c10 determines the frequency placement of the pole and zero. a typical value of c10 is between 100pf and 1000pf. when adding lag compensation, always check the loop stability by monitoring the transient response to a pulsed output load. the circuit of figure 1 works well without compensation. the circuit of figure 9 uses lag compensation to allow higher value fb divider resistors, at the expense of transient response speed, potentially requiring higher value output capacitors (see typical operating characteristics ). using one of these two circuits is recommended. using compensation for improved soft-start the digital soft-start of the main step-up regulator limits the average input current during startup. if even smoother startup is needed, add a low-frequency lead compensation network (figure 9). the improved soft- start is active only during startup when the output volt- age rises. positive changes in the output are instantaneously coupled to the fb pin through d1 and feed-forward capacitor c9. this arrangement generates a smoothly rising output voltage. when the output volt- age reaches regulation, capacitor c9 charges up through r9 and diode d1 turns off. if desired, c9 and r9 can be chosen also to provide some lead compen- sation in normal operation. in most applications, lead compensation is not needed, and can be disabled by making r9 large. with r9 much greater than r7, the pole and the zero in the compensation network are very close to one another and cancel out after startup, elimi- nating the effect of the lead compensation. input capacitor the input capacitor (c in ) reduces the current peaks drawn from the input supply and reduces noise injec- tion into the device. a 10f ceramic capacitor is used in the standard application circuit (figure 1) because of the high source impedance seen in typical lab setups. actual applications usually have much lower source impedance since the step-up regulator often runs directly from the output of another regulated supply. typically, c in may be reduced below the values used in the standard applications circuit. ensure a low-noise supply at the in pin by using adequate c in . alter- natively, greater voltage variation can be tolerated on c in if in is decoupled from c in using an rc lowpass fil- ter (see r1, c1 in figure 1). rectifier diode the max1997/MAX1998s high switching frequency demands a high-speed rectifier. schottky diodes are rec- ommended for most applications because of their fast recovery time and low forward voltage. in general, a 1a schottky diode complements the internal mosfet well. f f p_lag z_lag = + + ? ? ? ? ? ? = 1 210 78 78 10 1 210 10 () r rr rr c rc f f z_lead p_lead = + = + ? ? ? ? ? ? 1 2799 1 29 78 78 9 () rr c r rr rr c
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 24 ______________________________________________________________________________________ input p-channel mosfet select the input p-channel mosfet based on current rating, voltage rating, gate threshold, and on-resis- tance. the mosfet must be able to handle the peak input current (see the inductor selection section). the drain-to-source voltage rating of the input mosfet should be higher than the maximum input voltage. because the mosfet conducts the full input current, its on-resistance should be low enough for good effi- ciency. use a logic-level or low-threshold mosfet to ensure that the switch is fully enhanced at the lowest input voltage. setting the input overcurrent threshold the high-side comparator of the max1997/MAX1998 provides input overcurrent protection when used in con- junction with an external p-channel mosfet p1. the accuracy of the overcurrent threshold is affected by many factors, including comparator offset, resistor toler- ance, input voltage range, and variations in mosfet r ds(on) . the input overcurrent comparator is only intended to protect against catastrophic failures. this function is similar to an input fuse. to minimize the impact of the comparator s input offset on the current-sense accuracy, the sense voltage should be close to the upper limit of the comparator s common-mode range (same as the operating range), which extends up to 80% of the input voltage. the resistive voltage divider r4/r5, combined with the on- state resistance of p1, sets the overcurrent threshold. the center of r4/r5 is connected to the inverting input (ocn) as shown in figure 10. if the comparator and resistors are ideal, the threshold is at the current where both inputs are equal: i l(max) is the average inductor current at maximum load condition and minimum input voltage, and is given by: where is the efficiency of the main step-up regulator. if the step-up regulator s minimum input voltage is 2.7v, the output voltage is 9v, and the maximum load current is 0.3a. assuming 80% efficiency, the maximum average inductor current is: r ds(max) is the maximum on-state drain-to-source resistance of p1. the maximum r ds(on) at +25 c can be found in the mosfet manufacturer s data sheet, but that number does not include the mosfet s tempera- ture coefficient. since the resistance temperature coef- ficient is 0.5%/ c, r ds(max) can be calculated with the following equation: r ds(max) = r ds_25c ? [1 + 0.005 ? (t j - 25)] where t j is the actual mosfet junction temperature in normal operation due to ambient temperature and self- heating caused by power dissipation. as an example, consider the fairchild fdn304p, which has a maximum r ds(on) at room temperature of 70m ? . if the junction temperature is +100 c, the maximum on-state resis- tance over temperature is: r ds(max) = 70m ? [1 + 0.005 ? (100 - 25)] = 100m ? for given r2 and r3 values, the ideal ratio of r4/r5 can be determined: r r rr r 4 5 23 3 1 = + v - i r v - in peak(max) ds(max) in i 9v 0.8 2.7v 0.3a = 25a l(max) = . 1 i v v i l(max) out in(min) load(max) = vv-ir in in l(max) ds(max) + = () + r rr r rr 3 23 5 45 figure 10. setting the overcurrent threshold v in p1 r ds(on) r5 r3 r4 r2 oc comp ocp ocn 100pf
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer ______________________________________________________________________________________ 25 after including the effects of resistor tolerance, com- parator offset, and input voltage variation, the minimum input overcurrent threshold equation is: where v in(min) is the minimum expected value of the input voltage, is the tolerance of the resistors, and 5mv is the worst-case input offset voltage of the comparator. to simplify the equation, define a constant (k) as follows: the minimum threshold equation becomes: solving for r4/r5 yields: the r4/r5 ratio guarantees the required minimum level for i l(max) . the typical overcurrent threshold is given by: the following example shows how to apply the above equations in the design. if 1% resistors are used, then = 0.01. to set v ocp to be around 75% of v in , select r2 = 51.1k ? and r3 = 150k ? . assume that the mini- mum input voltage is 2.7v and the typical input voltage is 3.3v, the average inductor current at maximum load is 1.25a, and the maximum r ds(on) of p1 is 100m ? : if r5 =150k ? , then r4 = 39.2k ? . the typical overcur- rent threshold is: charge pumps selecting the number of charge-pump stages for highest efficiency, always choose the lowest num- ber of charge-pump stages that meet the output requirement. the number of positive charge-pump stages is given by: where n pos is the number of positive charge-pump stages, v g_on is the positive linear-regulator (reg p) output, v main is the main step-up regulator output, v d is the forward voltage drop of the charge-pump diode, and v dropout is the dropout margin for the linear reg- ulator. use v dropout = 2v. the number of negative charge-pump stages is given by: where n neg is the number of negative charge-pump stages, v g_off is the negative linear-regulator (reg n) output, v main is the main step-up regulator output, v d is the forward-voltage drop of the charge-pump diode, and v dropout is the dropout margin for the linear reg- ulator. use v dropout = 2v. the above equations are derived based on the assumption that the first stage of the positive charge pump is connected to v main and the first stage of the negative charge pump is connected to ground. sometimes fractional stages are more desirable for bet- ter efficiency. this can be done by connecting the first stage to v in or another available supply. if the first charge-pump stage is powered from v in , then the above equations become: n v+v - v v - v n - v+v +v v - v pos g_on dropout in main d neg g_o ff dropout in main d = = 2 2 n - v+v v - v neg g_o ff dropout main d = 2 n v+v - v v - v pos g_on dropout main main d = 2 i 3.3v 0.047 - 1 (39.2k +1 ) (51.1k +1 ) th_typ = ? ? ? ? ? ? = ? ??? ??? 1 50 50 150 50 415 .a r4 r5 2.7v - 1.25a 0.1 2.7v - = + + ? ? ? ? ? ? ? ? ? ? = 0 9802 150 150 0 9802 51 1 0 005 1 0 2637 . .. . . ? ? ?? k v k == 1 - 0.01 1 + 0.01 0 9802 . i v r - r3 (r4 +r5) r5 (r2+r3) th_typ in(typ) ds(typ) = ? ? ? ? ? ? 1 r4 r5 v - i v - in(min) l(max) ds(max) in(min) = + + ? ? ? ? ? ? ? ? ? ? k r r rkr mv 3 32 5 1 vv- ir in(min) in(min) l(max) ds(max) + += + r kr r mv kr rkr 3 23 5 5 45 ( ) k = + + 1 1 v v- i r in(min) in(min) l(max) ds(max) + + + + + = + + + + r rr mv r rr 31 21 31 5 51 41 51 () () () ( ) () () () ? ?
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 26 ______________________________________________________________________________________ flying capacitors increasing the flying capacitor (c x ) value increases the output current capability. increasing the capacitance indefinitely has a negligible effect on output current capability because the internal switch resistance and the diode impedance limit the source impedance. a 0.1f ceramic capacitor works well in most low-current applications. the flying capacitor s voltage rating must exceed the following: v cx > n ? v main where n is the stage number in which the flying capaci- tor appears, and v main is the main output voltage. for example, the two-stage positive charge pump in the typical application circuit (figure 1) where v main = 9v contains two flying capacitors. the flying capacitor in the first stage (c25) requires a voltage rating greater than 9v. the flying capacitor in the second stage (c24) requires a voltage rating greater than 18v. charge-pump output capacitor increasing the output capacitance or decreasing the esr reduces the output ripple voltage and the peak-to- peak transient voltage. with ceramic capacitors, the output voltage ripple is dominated by the capacitance value. use the following equation to approximate the required capacitor value: where v ripple is the peak-to-peak value of the output ripple. charge-pump rectifier diodes use schottky diodes with a current rating equal to or greater than two times the average charge-pump input current. if the loaded charge-pump output voltage is greater than required, some or all of the schottky diodes can be replaced with low-cost silicon switching diodes with an equivalent current rating. the charge- pump input current is: i cp _ in = i cp _ out ? n where n is the number of charge-pump stages. linear-regulator controllers output voltage selection adjust the positive linear-regulator (reg p) output volt- age by connecting a resistive voltage-divider from v g_on to gnd with the center tap connected to fbp (figure 1). select r20 in the range of 10k ? to 30k ? . calculate r19 with the following equation: r19 = r20 [(v g_on / v fbp ) - 1] where v fbp = 1.25v. the output voltages of linear regulators reg 1 and reg 2 can be similarly adjusted. adjust the negative linear-regulator (reg n) output voltage by connecting a resistive voltage-divider from v g_off to ref with the center tap connected to fbn (figure 1). select r17 in the range of 10k ? to 30k ? . calculate r16 with the following equation: r16 = r17 [(v fbn - v g_off ) / (v ref - v fbn )] where v fbn = 125mv, v ref = 1.25v. ref can source up to 75a, using a resistor greater than 17k ? for r17 leaves at least 10a for other uses. pass transistor selection the pass transistor must meet specifications for current gain ( ), input capacitance, collector-emitter saturation voltage, and power dissipation. the transistor s current gain limits the guaranteed maximum output current to: where i drv is the minimum guaranteed base drive cur- rent, v be is the base-to-emitter voltage of the transistor, and r be is the pullup resistor connected between the transistor s base and emitter. furthermore, the transis- tor s current gain increases the linear regulator s dc loop gain (see the stability requirements section), so excessive gain destabilizes the output. therefore, tran- sistors with current gain over 100 at the maximum out- put current can be difficult to stabilize and are not recommended. the transistor s input capacitance and input resistance also create a second pole, which could be low enough to make the output unstable when heavily loaded. the transistor s saturation voltage at the maximum out- put current determines the minimum input-to-output voltage differential that the linear regulator supports. alternatively, the package s power dissipation could limit the usable maximum input-to-output voltage differ- ential. the maximum power dissipation capability of the transistor s package and mounting must exceed the actual power dissipation in the device. the power dissi- pation equals the maximum load current times the max- imum input-to-output voltage differential: p = i load(max) (v ldoin - v ldoout ) = i load(max) v ce ii v r load(max) drv be be min = ? ? ? ? ? ? ? c i v out load osc ripple 2f
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer ______________________________________________________________________________________ 27 stability requirements the max1997/MAX1998 linear-regulator controllers use an internal transconductance amplifier to drive an external pass transistor. the transconductance amplifi- er, the pass transistor, the base-emitter resistor, and the output capacitor determine the loop stability. the transconductance amplifier regulates the output voltage by controlling the pass transistor s base cur- rent. the total dc loop gain is approximately: where v t is 26mv at room temperature, h fe is the pass transistor s dc current gain, and i bias is the current through the base-to-emitter resistor (r be ). each of the four linear-regulator controllers is designed for a differ- ent maximum output current so they have different out- put drive currents and different bias currents (i bias ). each controller s bias current can be found in the electrical characteristics . the current listed in the conditions column for the fb_ regulation voltage specification is the individual controller s bias current. the base-to-emitter resistor for each controller should be chosen to set the correct i bias : the output capacitor and the load resistance create the dominant pole in the system. however, the internal amplifier delay, the pass transistor s input capacitance, and the stray capacitance at the feedback node create additional poles in the system, and the output capacitor s esr generates a zero. for proper operation, use the following steps to ensure the linear regulator stability: 1) first, calculate the dominant pole set by the linear regulator s output capacitor and the load resistor: where c ldo is the output capacitance of the ldo and r load is the load resistance corresponding to the maximum load current. the unity gain crossover of the linear regulator is: f crossover = a v(ldo) f pole(ldo) 2) the pole caused by the internal amplifier delay is at about 1mhz: f pole(amp) ? 1mhz 3) next, calculate the pole set by the transistor s input capacitance, the transistor s input resistance, and the base-to-emitter pullup resistor: because r be is much greater than r in , the above equation can be simplified: where g m is the transconductance of the pass tran- sistor, and f t is the transition frequency. both para- meters can be found in the transistor s data sheet. therefore, the equation can be further simplified: 4) next, calculate the pole set by the linear regulator s feedback resistance and the capacitance between fb_ and gnd (approximately 5pf including stray capacitance): and 5) next, calculate the zero caused by the output capacitor s esr: where r esr is the equivalent series resistance of c ldo . f cr esr zero ldo esr _ = 1 2 f cr r pole fb n fb ()_ (||) = 1 21617 f cr r f cr r f cr r pole fb p fb pole fb fb pole fb fb ()_ ()_ ()_ (||) (||) (|| ) = = = 1 21920 1 28899 1 21112 1 2 f f pole(cin) t = h fe f 1 c g h g pole(cin) ii m i fe m = == 2 2 cr f rr nn in t n f 1 i) pole(cin) be in = 2 cnr r ii ( f 1 pole(ldo) ldo load = 2 cr r v be be bias = i a 4 v h i v v(ldo) t bias fe load ref = ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 i
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 28 ______________________________________________________________________________________ 6) to ensure stability, choose cldo large enough so that the crossover occurs well before the poles and zero calculated in steps 2 to 5. the poles in steps 3 and 4 generally occur at several megahertz and using ceramic capacitors ensures the esr zero occurs at several megahertz as well. placing the crossover below 500khz is sufficient to avoid the amplifier-delay pole and generally works well, unless unusual component choices or extra capaci- tances move the other poles or zero below 1mhz. a capacitor connected between the regulator output and the feedback node can improve the transient response and reduce the noise coupled into the feedback loop (figure 1). if a low-dropout solution is needed, an external p-channel mos pass transistor can be used for reg 1. however, a pmos-based linear regulator requires higher output capacitance to stabilize the loop. the high gate capaci- tance of the p-channel mosfet lowers f pole(cin) and can cause instability. a large output capacitor must be used to reduce the unity-gain bandwidth and ensure that the pole is well above the unity-gain crossover frequency. a ceramic capacitor of at least 30f is recommended for v in = 2.7v, v out = 2.5v, and i load = 250ma. vcom buffer connect the inverting input fbnb directly to the output outb to configure the buffer as a voltage follower. adjust the buffer s output voltage by connecting a volt- age-divider from the gamma reference v gamma to gnd with the center tap connected to the noninverting input fbpb (figure 1). select r14 in the 10k ? to 100k ? range. calculate r13 with the following equation: the vcom buffer is designed to be stable with a 0.47f capacitor from outb to gnd. the charge and discharge currents of the vcom buffer output can be optimized by adding resistor r b in series with the lcd backplane load and a ceramic capacitor c b (1f or larger) in parallel with the backplane load (figure 11). start with a 10 ? resistor, then gradually increase the value of r b , balancing between display quality and buffer power dissipation. increasing the value of c b improves the efficiency of the vcom buffer. r13 = r14 v gamma fbpb v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 figure 11. optimizing vcom buffer drive current v gamma c b r b to tft lcd backplane vcom buffer 0.47 f figure 12. high-current loops of step-up regulator v out v in c out c in d ground impedance l figure 13. operation with output voltage >13v using cascoded mosfet max1997 MAX1998 step-up regulator pgnd v p v main 15v fb lx v in v n
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer ______________________________________________________________________________________ 29 applications information pc board layout and grounding careful pc board layout is extremely important for proper operation. use the following guidelines for good pc board layout: 1) the high-current loops of the main step-up regula- tors are shown in figure 12. minimize the area of these loops by placing the input bypass capacitors, output diode, and output capacitors less than 0.2in (5mm) from the lx and pgnd pins. connect these components with traces as wide as possible. avoid using vias in the high-current paths. if vias are unavoidable, use many vias in parallel to reduce resistance and inductance. 2) create islands for the analog ground (gnd), power ground (pgnd), and linear-regulator ground. connect all three ground areas (islands) at only one location, which is the backside pad of the device. the ref bypass capacitor and all feedback dividers should be connected to the analog ground island (gnd). the step-up regulator s input and output capacitors, and the charge-pump components should be a wide power ground plane. the power ground plane should be connected to the power ground pin (pgnd) with a wide trace. maximizing the width of the power ground traces improves effi- ciency and reduces output voltage ripple and noise spikes. all the other ground connections, such as the in pin bypass capacitor and the linear-regulator output capacitors, should be star-connected to the backside of the device with wide traces. make no other connections between these separate ground planes. 3) place the in pin and ref pin bypass capacitors as close to the device as possible. 4) place all feedback voltage-divider resistors as close to their respective feedback pins as possible. the divider s center trace should be kept short. placing the resistors far away causes their fb traces to become antennas that can pick up switch- ing noise. care should be taken to avoid running any feedback trace parallel to its associated drive trace or near lx or the switching nodes in the charge pumps. 5) minimize the length and maximize the width of the traces between the output capacitors and the load for best transient responses. 6) minimize the size of the lx node while keeping it wide and short. keep the lx node away from feed- back nodes (fb, fbp, and fbn) and analog ground. use dc traces as a shield, if necessary. large ground planes on a multilayer board can pro- vide additional shielding. refer to the max1997 evaluation kit for an example of proper board layout. additional application circuits operation with main output voltage >13v the maximum output voltage of the step-up regulator is 13v, which is limited by the absolute maximum rating of the internal power mosfet. to achieve higher output voltage, an external n-channel mosfet can be cas- coded with the internal fet (figure 13). since the gate of the external fet is biased from the input supply, use a logic-level fet to ensure that the fet is fully enhanced at the minimum input voltage. the current rating of the fet needs to be higher than the internal current limit. disabling input mosfet switch if the input protection mosfet is not needed, disable the input overcurrent comparator by connecting the ocp pin to ground, and the ocn pin to ref. leave the gate pin floating (figure 14). figure 14. disabling input mosfet switch max1997 MAX1998 step-up regulator switch control ref ref gate 3.3v to 5v ocn ocp ocn gnd pgnd v p v main +9v fb lx in v in v n
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer 30 ______________________________________________________________________________________ chip information transistor count: 4704 32 31 30 29 28 27 26 shdn freq ondc in pflt gate ocp 25 ocn 9 10 11 12 13 14 15 drvn fbn drva ref gnd fbnb outb 16 v ddb 17 18 19 20 21 22 23 fbpb fb2 drv2 fb fbp drvp lx 8 7 6 5 4 3 2 on2 onp onn ct fb1 drv1 pgnd max1997 thin qfn 5mm 5mm 1 tgndb 24 tgnda top view pin configurations (continued)
max1997/MAX1998 quintuple/triple-output tft lcd power supplies with fault protection and vcom buffer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 31 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. qfn thin 5x5x0.8 .eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a 0.15 c b 0.15 c a document control no. 21-0140 package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm proprietary information approval title: c rev. 2 1 e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 l d/2 d2/2 l c l c e e l c c l k k l l 2 2 21-0140 rev. document control no. approval proprietary information title: common dimensions exposed pad variations 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220. notes: 10. warpage shall not exceed 0.10 mm. c package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

▲Up To Search▲

Price & Availability of MAX1998

	To Download MAX1998 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .